Program

NOCS, as part of the 2023 edition of Embedded Systems Week, will take place on the campus of the Hamburg University of Technology (TUHH). In particular, the Symposium will be held in Building H, Room H0.16 - Ditze Lecture Hall.

A campus plan of the TUHH can be found here. More details are available at https://esweek.org/.

Thursday - September 21, 2023
Time (CEST)	Activity
09:00 - 09:10	Opening Remarks Chair: Mahdi Nikdast (Colorado State University)
09:10 - 10:00	Keynote I: "Connecting Artificial Neural Networks" Speaker: Axel Jantsch (TU Wien) Chair: Mahdi Nikdast (Colorado State University)
10:00 - 10:30	COFFEE BREAK
10:30 - 12:30	Technical Session I: "High-Performance and Dynamic NoC Architectures" Chair: Masoumeh (Azin) Ebrahimi (KTH Royal Institute of Technology)
10:30	FlooNoC: A Multi-Tbps Wide NoC for Heterogeneous AXI4 Traffic Tim Fischer, Michael Rogenmoser, Matheus Cavalcante, Frank Gurkaynak, and Luca Benini ETH Zurich DOI: 10.1109/MDAT.2023.3306720
11:00	Dynamically Reconfigurable Network Protocol for Shape-Changeable Computer System Shun Nagasaki, Junichiro Kadomoto, Hidetsugu Irie and Shuichi Sakai University of Tokyo DOI: 10.1109/MDAT.2023.3309891
11:30	PiN: Processing in Network-on-Chip (Tutorial Paper) Zhonghai Lu KTH Royal Institute of Technology DOI: 10.1109/MDAT.2023.3307943
12:30 - 13:30	LUNCH BREAK
13:30 - 15:00	Technical Session II: "NoCs for AI Acceleration and Interposer Systems" Chair: Zhonghai Lu (KTH Royal Institute of Technology)
13:30	A NoC-Based Spatial DNN Inference Accelerator with Memory-Friendly Dataflow Lingxiao Zhu, Wenjie Fan, Chenyang Dai, Shize Zhou, Yongqi Xue, Zhonghai Lu, Li Li, and Yuxiang Fu Nanjing University DOI: 10.1109/MDAT.2023.3310199
14:00	ELEMENT: Energy-efficient Multi-NoP Architecture for IMC-based 2.5D Accelerator for DNN Training Neethu K¹, Sharin Shahana K C², Rekha K. James¹, John Jose³, and Sumit K. Mandal² ¹ Cochin University of Science and Technology, Cochin ² Indian Institute of Science, Bangalore ³ Indian Institute of Technology, Guwahati DOI: 10.1109/MDAT.2023.3309743
14:30	SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs Gabriele Tombesi¹, Joseph Zuckerman¹, Paolo Mantovani¹, Davide Giri¹, Maico Cassel dos Santos¹, Tianyu Jia², David Brooks², Gu‑Yeon Wei², and Luca Carloni¹ ¹ Columbia University ² Harvard University [Best-Paper Award Candidate] DOI: 10.1109/MDAT.2023.3310355
15:00 - 15:30	COFFEE BREAK
15:30 - 17:00	Technical Session III: "Routing and Deadlock Recovery in Interconnection Networks" Chair: Felipe Gohring (École Polytechnique Montréal)
15:30	A Reinforcement Learning Framework with Region-Awareness and Shared Path Experience for Efficient Routing in Networks-on-Chip Kamil Khan and Sudeep Pasricha Colorado State University DOI: 10.1109/MDAT.2023.3306719
16:00	SPOCK: Reverse Packet Traversal for Deadlock Recovery Zeyu Chen, Ankur Bindal, Vaidehi Garg, and Tushar Krishna Georgia Institute of Technology [Best-Paper Award Candidate] DOI: 10.1109/MDAT.2023.3309742
16:30	Similarity-based Fast Analysis of Data Center Networks Shruti Yadav Narayana¹, Emily Shriver², Kenneth Norman Lee O'Neal¹, Nuriye Yildirim¹, Khamida Begaliyeva¹, and Umit Ogras¹ ¹ University of Wisconsin-Madison ² Intel DOI: 10.1109/MDAT.2023.3310450
18:15 - 23:15	RECEPTION & SOCIAL DINNER The networking event, which will also be MEMOCODE's social event, will start at 18:15 with a reception and continue with a buffet dinner from 19:15 to 23.15. Location: Restaurant Leuchtturm - Außenmühlendamm 2 21077 Hamburg-Harburg Restaurant Leuchtturm webpage Directions from TUHH campus

Friday - September 22, 2023
Time (CEST)	Activity
09:00 - 10:00	Keynote II: "Networks-on-Chip for Reconfigurable Computing Systems" Speaker: Diana Göhringer (TU Dresden) Chair: Mahdi Nikdast (Colorado State University)
10:00 - 10:30	COFFEE BREAK
10:30 - 12:30	Technical Session IV: "NoC Modeling, Optimization, and Verification" Chair: Alireza Monemi (Barcelona Supercomputing Center)
10:30	Fast Analysis using Finite Queuing Model for Multi-layer NoCs Shruti Yadav Narayana, Sumit Mandal, Raid Ayoub, Mohammad Majharul Islam, Michael Kishinevsky, and Umit Ogras ¹ University of Wisconsin-Madison ² Intel DOI: 10.1109/MDAT.2023.3310167
11:00	edAttack: Hardware Trojan Attack on On-Chip Packet Compression Atul Kumar¹, Dipika Deb², Shirshendu Das³, and Palash Das⁴ ¹ Indian Institute of Technology, Ropar ² Indian Institute of Technology, Guwahati ³ Indian Institute of Technology, Hyderabad ⁴ Indian Institute of Technology, Jodhpur DOI: 10.1109/MDAT.2023.3306718
11:30	Analytical Model for Performance Evaluation of Token-Passing Based WiNoCs Ibrahim Krayem, Joel Ortiz Sosa, Cedric Killian, and Daniel Chillet University of Rennes 1 DOI: 10.1109/MDAT.2023.3309730
12:30 - 13:30	LUNCH BREAK
13:30 - 15:00	Special Session on "New Architectures and Techniques for Edge Intelligence" Chair: Sudeep Pasricha (Colorado State University)
13:30	On Hardware-Aware Design and Optimization of Edge Intelligence Shuo Huai¹, Hao Kong¹, Xiangzhong Luo¹, Di Liu², and Weichen Liu¹ ¹ Nanyang Technological University ² Norwegian University of Science and Technology DOI: 10.1109/MDAT.2023.3307558
14:00	Hardware/Software Co-Exploration for Hyperdimensional Computing on Network-on-Chip Architecture Junhuan Yang, and Lei Yang George Mason University DOI: 10.1109/MDAT.2023.3309733
14:30	Automated Optical Accelerator Search: Expediting Green and Ubiquitous DNN-Powered Intelligence Mingfeng Lan¹, Mengquan Li¹, Jie Xiong¹, Weichen Liu², Chubo Liu¹, and Kenli Li¹, ¹ Hunan University ² Nanyang Technological University DOI: 10.1109/MDAT.2023.3309895
15:00 - 15:30	COFFEE BREAK
15:30 - 17:00	Closing Session and Panel
15:30	NOCS 2023 Best-Paper Award
16:00	Interconnects in the Post-Moore Era: Challenges and Opportunities Organizers & Moderators: Abhijit Das (Universitat Politècnica de Catalunya) and Sergi Abadal (Universitat Politècnica de Catalunya) Panelists: Marilyn Wolf (University of Nebraska-Lincoln), Sudeep Pasricha (Colorado State University), Masoumeh (Azin) Ebrahimi (KTH Royal Institute of Technology), and Saïd Derradji (Arteris)
16:55	Closing Remarks

Keynote Talks

Keynote I

Date: Thursday - September 21, 2023
Time: 9:00 - 10:00 CEST
Speaker: Axel Jantsch (TU Wien)
Title: Connecting Artificial Neural Networks
Chair: Mahdi Nikdast (Colorado State University)

Abstract:
Architectures for accelerating the execution of artificial neural networks proliferate, be it for convolutional, recurrent or spiking, large language or diffusion models. These algorithms have exceedingly high demands on computation, memory and communication. This talk will review and analyze the communication needs and proposed architectures for popular ANNs, highlight recent trends and discuss possible future developments.

Bio:

Axel Jantsch graduated from TU Wien, Vienna, Austria, and was with The Royal Institute of Technology, KTH in Stockholm 1997-2014. Since 2015 he is Prof. in Systems on Chip at TU Wien, Vienna, Austria. He pioneered early NoC architectures and his group at developed the Nostrum NoC in the period 2000-2008. Since 2019 he leads a large project on Embedded Machine Learning at TU Wien, he studies efficient realizations of Deep Neural Networks in embedded devices.

⇧ Back to the first-day program

Keynote II

Date: Friday - September 22, 2023
Time: 9:00 - 10:00 CEST
Speaker: Diana Göhringer (TU Dresden)
Title: Networks-on-Chip for Reconfigurable Computing Systems
Chair: Mahdi Nikdast (Colorado State University)

Abstract:
Nowadays, Networks-on-Chip (NoCs) are a core component for the communication in multi- and many-core computing systems. Also in reconfigurable computing systems, such as Field Programmable Gate Arrays (FPGAs) and Coarse-Grained Reconfigurable Arrays (CGRAs), NoCs play an important role for the communication infrastructure between the processing elements. The design space, e.g. limited resources and dynamic reconfiguration, offer other advantages in terms of degree of freedom at design- and runtime compared to traditional ASICs.
This talk will give an overview of NoCs for FPGAs and CGRAs, the current challenges in this domain as well as an outlook to future research trends.

Bio:

Diana Göhringer is professor and holds the Chair of Adaptive Dynamic Systems at Technische Universität Dresden since 2017. She received her Ph.D. (summa cum laude) in Electrical Engineering and Information Technology from the Karlsruhe Institute of Technology (KIT), Germany in 2011. She is author and co-author of over 200 publications in international journals, conferences and workshops. She serves as technical program committee member in several international conferences and workshops (e.g. DATE, ICCAD, FPL). She is reviewer and guest editor of several international journals. Furthermore, she is a member of IEEE, ACM and HIPEAC. Her research interests include reconfigurable computing, multiprocessor systems-on-chip (MPSoCs), networks-on-chip, simulators/virtual platforms, hardware-software codesign and runtime systems.

⇧ Back to the second-day program

Panel

Date: Friday - September 22, 2023
Time: 16:00 - 17:00 CEST
Title: Interconnects in the Post-Moore Era: Challenges and Opportunities
Organizers & Moderators: Abhijit Das (Universitat Politècnica de Catalunya) and Sergi Abadal (Universitat Politècnica de Catalunya)
Panelists: Marilyn Wolf (University of Nebraska-Lincoln), Sudeep Pasricha (Colorado State University), Masoumeh (Azin) Ebrahimi (KTH Royal Institute of Technology), and Saïd Derradji (Arteris)

Abstract:
We are entering a new golden age of computer architecture, which is challenging but also full of opportunities. The looming end of Moore's law compels everyone to conceive future computing systems once transistors reach their limits. Some leading approaches in this direction are the chiplet paradigm, domain customisation, quantum computing, etc. However, these architectural and technological innovations have shifted the fundamental bottleneck from computation to communication. Hence, on-chip and on-package interconnects will play a pivotal role in determining the performance, efficiency and scalability of future computing systems. The goal of this panel is to discuss about interconnects of the post-Moore era. It will provide insights into the design considerations, challenges, and potential solutions for developing interconnects for the emerging approaches to mitigate the effects of the end of Moore's law.